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signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 features ? ntsc/pal compatible ? composite/s-video input selection mux ? integrated dual analog signal path ? adjustable internal anti-alias filters ? internal clamp circuits ? automatic gain control ? integrated reference voltage source for spt7852 ? matched voltage output range for driving spt7852 block diagram applications ? high-end ntsc/pal video decoding ? high quality s-video decoding ? video frame grabbing ? professional video ? vcr signal capture ? security cameras general description the spt9210 is the analog front-end processing chip for the spt video decoder chip set. the video decoder chip set is an integrated three chip solution for high quality video signal decoding of ntsc/pal composite video and s-video for- mats at 8.9 effective number of bits of dynamic performance. the spt9210 is a fully integrated analog video processor chip capable of processing standard video signals in either a single-channel composite video input mode or a dual-chan- nel s-video (component y/c) input mode. as part of the chip set, the spt9210 is specially designed to easily interface to the downstream spt7852 dual 10-bit analog-to-digital con- verter (see figure 1.) spt9210 analog video processor a a a a a a a a a a 19 17 4 18 10 2 3 20 9 7 8 12 13 11 a a a a a a a a a a clamp clamp bias bias sw low pass filter low pass filter sync separation automatic gain control automatic gain control gain detect delay clamp clamp 3x 3x voltage regulator frequency adjustment vref 1 16 15 14 6 5 select sw input y input c vcc input y/c gnd vref vref clamp filter adj. vrl adjust vrl force vrl sense vrh sense vrh force vrh adjust output c output y c-clamp c c-agc c-clamp y the spt9210 provides luminance and chrominance channel dc restoration, anti-alias filtering, automatic gain control and signal offset and gain to match the front-end requirements of the spt7852 dual 10-bit analog-to-digital converter. in addition to performing the analog processing of the video signal before data conversion, the spt9210 also provides the voltage reference sources for the spt7852. the spt9210 is available in a 20-lead soic package and operates over the commercial temperature range. it requires a single +5 v supply and dissipates 620 mw of power.
spt 2 11/7/97 spt9210 electrical specifications t a =+25 c, v in =1.0 v p-p , v cc =+5.0 v, unless otherwise specified. test test parameters conditions level min typ max units video signal output y/c output amplitude (pin 14) composite/s-video mode 2.5 v p-p c output amplitude (pin 6) s-video mode 0.7 v p-p differential gain composite/s-video mode 0.5 % differential phase composite/s-video mode 0.5 degrees automatic gain control y/c output amplitude (pin 14) v in =+3 db 2.5 v composite/s-video mode y/c output amplitude (pin 14) v in =-6 db 2.5 v composite/s-video mode c output amplitude (pin 6) v in =+3 db 0.7 v s-video mode c output amplitude (pin 6) v in =-6 db 0.7 v s-video mode clamp circuit sync tip offset level composite/s-video mode 1.0 v c output bias voltage s-video mode 2.5 v anti-alias filter chrominance signal side frequency response f in =3 mhz, v in =0 db 7.96 db frequency response f in =5 mhz, v in =0 db 4.96 db voltage reference v rh (top of ladder) i out =+5 ma 3.6 v v rl (bottom of ladder) i out =+5 ma 1.0 v digital input (select sw pin 1) logic 1 voltage 2.0 v logic 0 voltage 0.8 v power supply supply current i cc no signal 70 ma supply voltage v cc 4.75 5.75 v absolute maximum ratings (beyond which damage may occur) 1 supply voltage v cc ........................................................................... +6 v temperature operating temperature ................................. 0 to +70 c junction temperature ......................................... +175 c lead temperature, (soldering 3 seconds) .......... +320 c storage temperature ................................ -55 to +150 c note: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied conditions in typical applications. test level codes all electrical characteristics are subject to the follow- ing conditions: all parameters having min/max speci- fications are guaranteed. the test level column indicates the specific device testing actually per- formed during production and quality assurance in- spection. any blank section in the data column indi- cates that the specification is not tested at the speci- fied condition. test procedure 100% production tested at the specified temperature. 100% production tested at t a = +25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = +25 c. parameter is guaranteed over specified temperature range. test level i ii iii iv v vi
spt 3 11/7/97 spt9210 figure 1 - spt video decoder chip set spt video chip set application the spt9210 is the front-end analog video processor for the spt ntsc/pal video decoder chip set. this chip set, as shown in figure 1, is comprised of three monolithic chips, which together provide an overall integrated video decoding function- ality at 8.9 effective number of bits of dynamic performance. the full set includes the spt9210 analog video processor, the spt7852 dual 10-bit analog-to-digital converter and the spt2110 ntsc/pal video decoder. the spt9210 is specifi- cally designed to process video input signals so as to attain optimal data conversion by the spt7852 analog-to-digital converter. data sheets describing the overall chip set and the other components are available by contacting the factory. spt9210 general description the spt9210 is a fully integrated analog video processor chip capable of processing standard video signals in either a single-channel composite video input mode or a dual-chan- nel s-video input mode. standard 1 v p-p video signals are amplified to match the optimal drive requirements of the spt7852 dual 10-bit analog-to-digital converter. input selection as the typical interface circuit shows in figure 3, the mux selector pin (pin 1) controls selection between composite and s-video (component y/c). this is a ttl-level input. when composite video is selected (pin 1 high), the composite signal (pin 19) is fed into the luminance channel, and the chromi- nance channel is internally biased (i.e., no input is sourced). when s-video is selected (pin 1 low), the s-video luminance signal (pin 2) is fed into the luminance channel, and the s- video chrominance signal (pin 3) is fed into the chrominance channel. in addition to pin 19, another composite video signal can be applied to input pin 2. pin 1 selects which video signal is to be processed. (pin 1 high selects input from pin 19.) when operating with composite video on pin 2, decouple pin 3 to ground with a 0.1 m f capacitor (the chrominance input for s- video). this will reduce the noise produced on this input. a register or ttl buffer can drive pin 1 (video select switch). an optional transistor circuit is shown in figure 3. it is driven by the pin 1 signal with the collector tied to pin 3. it is used to reduce crosstalk that may occur when both composite and s- video signals are operating simultaneously. the transistor circuit is only necessary if both signals are present. all input video signals should be terminated with 75 w resistors and ac coupled to the spt9210 with a 0.47 m f capacitor. internal clamp, bias and sync detection the signals fed into the luminance channel (pins 2 and 19), which are either a composite signal or a luminance (y) signal, are internally dc restored to 2.0 v by an internal clamp circuit. note that this is not the final output clamp voltage as dis- cussed in the final dc clamp and gain stages section. the chrominance signal (pin 3) is biased to 2.5 v by an internal bias circuit. the luminance signal path has a sync separation circuit that compares the sync signal to a detection threshold and generates internal gain control and output clamping control signals. these timing signals are used to control internal sampling of the sync tip amplitude by the automatic gain control circuit. (see the automatic gain control discussion.) trap filter y/c separator (comb) luma processing chroma processing timing generation control parameter registers color space conversion 10-bit adc 10-bit adc aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa 2x clock mpu interface hsync vsync hblnk vblnk odd 9 9 b u f b u f output enable reset ref ladder timing pixel clock reset 13 r y g cr/cb b 5 8 8 8 ext adj clamp lpf agc clamp lpf agc adc vref aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa composite video signal s-video y signal s-video c signal select 2 5 bias sync det spt2110 spt7852 spt9210 m u x m u x m u x m u x
spt 4 11/7/97 spt9210 anti-alias filters both luminance and chrominance video signal paths have an anti-alias filter with a cut-off frequency of approximately 4.8 mhz. the cut-off frequency can be changed by an external resistor value. the relationship between the external resistance value and the cut-off frequency is shown in the typical performance curves section. automatic gain control the spt9210 performs automatic gain control (agc) of the composite/luminance and chrominance signals. the hori- zontal sync signal level is used as a reference for control of the signal gain. the chrominance signal gain is slaved to the luminance gain value. the gain circuitry can operate over an input voltage range of v in = -6 db to +3 db (where 1 v p-p = 0 db). the agc will maintain a 2.5 v p-p amplitude on the composite/luminance signal output and 0.7 v p-p amplitude on the chrominance signal output. the agc settling time can be adjusted via an external capacitor. spt recommends using a 0.47 m f capaci- tor for most conditions. in cases where extreme fluctuation is possible, a diode inserted between pins 7 and 16 will restrict the maximum control voltage. this will serve to reduce recovery time. final dc clamp and gain stages after the clamp, low pass filtering and automatic gain control functions are performed. each signal path is clamped to a fixed dc value and amplified to the proper voltage range for input into the spt7852 analog-to-digital converter. the analog sync signal is retained in the output of the spt9210 and passed on to the spt7852 and spt2110 ntsc/pal video decoder. for the composite/luminance output, the horizontal sync level is clamped to +1 v, and the full-scale amplitude of the composite luminance signal (including sync tip) is set to 2.5 v p-p amplitude by the agc. (see figure 2.) the generated signal is optimized for spt7852 performance (+1.0 to +3.5 v input range). the chrominance output signal is biased to +2.5 v and a 0.7 v p-p full-scale amplitude is maintained by the agc. the output drive circuit is optimized for interface to the spt7852. when driving loads other than the spt7852 (which have a capacitance >tbd m f), it may be necessary to insert a series resister between the output and the load so as to avoid oscillation. on-chip voltage references in addition to performing the analog processing of the video signal before data conversion, the spt9210 also provides the voltage reference sources (force and sense for the top and bottom of the reference ladder) required by the spt7852. this eliminates the need for external reference sources. a source of +3.5 v is provided to the top of the reference ladder and +1.0 v is provided to the bottom. pin 7 is the v l reference force pin and is tied to pin 4 of the spt7852. pin 13 is the v h reference force pin and is tied to pin 1 of the spt7852. a 240 w resistor should be tied between pin 7 and pin 13 on the spt9210. pin 8 is the v l reference sense pin and is tied to pin 3 of the spt7852. pin 8 is the v h reference sense pin and is tied to pin 2 of the spt7852. the values of v l and v h can be adjusted by changing the external resistor values at pins 9 and 11, respectively. the curves in the typical performance curve section show the voltage reference output values versus the external resis- tance values. the typical values for nominal +1.0 v and +3.5 v operation on v l and v h are approximately 10 k w and 25 k w , respectively. the v ref clamp pins need decoupling capacitors as shown in figure 3. each pin should have a 0.1 m f and 10 m f capacitor connected in parallel for proper decoupling. other information the spt9210 is available in a 20-lead soic package and operates over the commercial temperature range. it requires a single +5 v supply and dissipates 620 mw of power. figure 2 - composite/luminance signal i/o relationship 1.0 vpp spt9210 3.5 v 1.0 v 0.0 v pin 2 pin 19 pin 14 input signal output signal composite signal y signal composite/y output
spt 5 11/7/97 spt9210 figure 3 - typical interface circuit aaaaaaaaaa 1 9 +a 5 10 ? 1 7 4 1 8 1 0 2 3 2 0 75 w 0.47 ? 75 w 0.47 ? 75 w 0.47 ? 9 8 1 3 1 1 5 k w 10 k w aaaaaaaaaa clam p clam p bia s bia s sw low pass filter low pass filter sync separation automatic gain control automatic gain control gain detect dela y clam p clam p 3 x 3 x voltage regulator frequency adjustment v re f 1 1 6 1 5 1 4 6 5 25 k w c-clamp-y 0.68 f 500 k w to v rl pin 7 (spt9210) 0.47 f high: composite low: s-video v in = 1.0 v p- p composite signal input s-video y-signal input s-video c-signal input v re f v ref clamp filter- adj v rl - adj v rl sense to spt7852 pin 3 v rl force to spt7852 pin 1 240 w c-clamp-c 0.68 f 500 k w c-signal output to spt7852 pin 8 y/c-signal output to spt7852 pin 6 vcc 100 w 4.7 k w buffe r c-agc 1n91 4 1 2 v rl sense to spt7852 pin 2 7 v rl force to spt7852 pin 4 v rh - adj gn d * * * 0.1 f and 10 f in parallel ?optional ciruit (see text) * *
spt 6 11/7/97 spt9210 terminal explanations pin name voltage 1 select sw 1.4 v when this terminal is open or high, it is in the composite mode. when this terminal is low, it is in the s-video mode. pin name voltage 2 input y 2.0 v this terminal is the luminance signal input of the s-video mode. the clamp circuit fixes the sync/bottom voltage to 2.0 v. pin name voltage 3 input c 2.5 v this terminal is the chrominance signal input for s-video mode. the bias circuit fixes the center voltage to 2.5 v. pin name voltage 4v ref 2.5 v this terminal is the bypass capacitor connection for the internal reference voltage circuit. 5 k w 2 k w v cc 50 a 1 2 v cc v cc v cc v cc v cc v_clamp = 2.0 v + - v cc v cc v cc 3 v ref = 2.5 v 1 k w + - 4 v cc v cc v cc 10 k w 40 k w v_bg = 1.2 v pin name voltage 5 c-clamp c 1.5 v this terminal connects the capacitor that determines the time constant of the chrominance clamp circuit. pin name voltage 6 output c 2.5 v this terminal is the chrominance signal output. pin name voltage 7 vrl force 1.0 v 8 vrl sense 1.0 v 9 vrl adjust 0.6 v these terminals are the reference voltage sources for the adc on the low side. they are the output, sense and adjustment terminals. v cc 5 + - + - clk signal clamp voltage from agc 10 k w 2 k w 2 k w to final amp v cc + - 6 + - v cc agc clamp 6 k w 3 k w 4.8 ma v cc v cc 7 7.5 k w 15 k w v cc v_bg = 1.2 v v cc 8 9 buffer amp + -
spt 7 11/7/97 spt9210 terminal explanations - continued pin name voltage 10 ground 0.0 v pin name voltage 11 v rh adjust 3.6 v 12 v rl sense 3.6 v 13 v rl force 3.6 v these terminals are the reference voltage sources for the adc on the high side. they are the output, sense and adjustment terminals. pin name voltage 14 output y 2.5 v this terminal is the luminance signal output. pin name voltage 15 c-clamp y 0.6 v this terminal connects the capacitor that determines the time constant of the luminance clamp circuit. pin name voltage 16 c-agc 0.6 v this terminal connects the capacitor that determines the time constant of the agc circuit. pin name voltage 17 filter adjust 0.7 v this terminal is the fc adjustment of the internal low pass filter. pin name voltage 18 v ref clamp 2.0 v this terminal is the bypass capacitor connection for the internal reference voltage circuit. pin name voltage 19 input y/c 2.0 v this terminal is the input of the composite signal. the clamp circuit fixes the sync/ bottom voltage to 2.0 v. pin name voltage 20 v cc 5.0 v this terminal is the power supply. inner voltage reference (2.0 v) v cc 25.5 k w 30 k w v cc v cc 11 13 12 buffer amp + - v cc 1.7 k w 20 k w 14 + - v cc agc clamp 6 k w 3 k w 4.8 ma v cc v cc 15 + - + - clk signal clamp voltage from agc 10 k w 2 k w 2 k w to final amp v cc + - v cc 16 + - + - dly signal agc voltage 10 k w 3.6 k w + - v cc v cc clamp to final amp to ag c v cc 7 k w v cc v_bg = 1.2 v v cc 17 v cc to filter control v cc v cc inner voltage reference (2.0 v) v cc 18 19 v cc v cc v cc v cc v cc v_clamp = 2.0 v + -
spt 8 11/7/97 spt9210 s-video v in vs sync, bar 0 20 60 80 100 120 -6 -4 -2 0 +2 sync, bar (ire) v in (db) 40 bar sync composite v in vs sync, bar 0 20 60 80 100 120 -6 -4 -2 0 +2 sync, bar (ire) v in (db) 40 bar sync typical performance curves radj vs v rh (pin 12) 3.2 3.3 3.4 3.5 3.6 3.7 0 20406080100 v rh (v) radj (k w ) radj vs v rl (pin 8) 0.8 0.9 1.0 1.1 1.2 1.3 0 20406080100 v rl (v) radj (k w ) reference voltage characteristics video signal characteristics
spt 9 11/7/97 spt9210 f in vs delay, gain -150 -50 +50 +150 +250 0.1 1 10 100 delay (nsec) f in (mhz) aa aa aa aa aa aaa aa aa aa aa aa aa a a gain delay -70 -50 -30 -10 +10 gain (db) typical performance curves v in vs differential phase -2.0 -1.0 0 +1.0 +2.0 -6 -4 -2 0 +2 dp (degrees) v in (db) s-video composite f in vs v out -30 -20 -10 0 +10 0.1 1 10 100 v out (db) f in (mhz) 0k 5k 10k 20k 30k v in vs differential gain -20 -15 -10 -5 0 5 -6 -4 -2 0 +2 dg (%) v in (db) s-video composite low-pass filter characteristics
spt 10 11/7/97 spt9210 1 20 c g a b de f h i package outline 20-lead soic inches millimeters symbol min max min max a 0.165 0.181 4.2 4.6 b 0.224 0.248 5.7 6.3 c 0.394 0.409 10.0 10.4 d 0.039 typ 1.0 typ e 0.010 0.018 0.25 0.45 f 0.000 0.008 0.0 0.2 g 0.047 0.071 1.2 1.8 h 0.002 0.010 0.05 0.25 i 0.012 0.028 0.3 0.7
spt 11 11/7/97 spt9210 signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited . warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, ca n be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty. name i/o function select i selects video input source (high = composite video or low = s-video) input y i luminance signal input input c i chrominance signal input v ref - internal reference by-pass c-clamp c i chrominance clamp time constant capacitor output c o chrominance signal output v rl force o voltage reference low output (force) v rl sense o voltage reference low output (sense) v rl adjust i voltage reference low adjustment gnd i ground v rh force o voltage reference high output (force) v rh sense o voltage reference high output (sense) v rh adjust i voltage reference high adjust- ment output y o luminance signal output c-clamp y i luminance clamp time constant capacitor c-agc i automatic gain control time constant capacitor filter adj. i adjustment for fc of low pass filter v ref clamp - internal reference bypass input y/c i composite signal input v cc i +5 v power supply pin functions v rh force output y 1 2 3 16 15 14 4 5 6 7 8 9 10 11 12 13 17 18 19 20 v ref clamp filter adjust c-clamp y c-agc v rh adjust v rh sense v cc input y/c input c v ref output c v rl force v rl sense c-clamp c gnd v rl adjust select input y pin assignments 20l soic ordering information part number description temperature range package type SPT9210SCS analog video processor 0 to +70 c 20l soic

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